Here's a quick and dirty guide to implementing and downloading a project onto your Spartan-3E board. This guide assumes you've already created a Xilinx ISE project.


Project settings

First, make sure the project is set up for the right device. The top level in the sources hierarchy should show "xc3s500e-4fg320". If not, right click on it, choose "Properties", and change these settings:

Product Category=All (or General Purpose)
Family=Spartan3E
Device=XC3S500E
Package=FG320
Speed=-4





Adding constraints

One way to map FPGA pins to your verilog module is by using the method you learned in ECE3700 (create new constraints file, look up pin numbers in the manual, enter them in by hand...) Here's a link to the Spartan-3E Starter Kit Board User Guide, containing all the pin assignments for the board.

Instead of looking up pin numbers, there's is an alternate (easier?) method you can use. You'll notice at the end of that PDF, there is a sample constraints (UCF) file with all the pin numbers typed in for you. You can get the .UCF file HERE. Save this to your project folder and add it to the project (right click in the sources window, "Add Source...")

You will need to make your module I/O names match the names in the UCF file. Edit the .UCF file by clicking on the .UCF in the sources window, and double clicking on "Edit Constraints (text)" in the process window.





If you try to implement the design as it is now, you'll get lots of errors about unconnected pins. One way to fix this is by removing all the lines in the .UCF file for pins you're not using. Instead, it's easier to tell the software to ignore the unused pins: Select the top source file in the sources window. Right click on "Implement Design", choose "Properties", and check the box labeled Allow unmatched LOC Constraints.





Loading your design onto the board

Before you generate a programming file, you should change its startup clock to JTAG. This isn't required, but you'll see warnings about it later if you don't. Go to Generate Programming File -> Properties -> Startup Options and change the FPGA Start-Up Clock option to JTAG Clock.





Plug in your board and turn it on (there's a power switch next to the power jack). Double click Configure Device (iMPACT) (under Generate Programming File). This may pop up another window, go with its defaults (Configure devices using JTAG, Automatically connect to a cable) and click Finish.







Click on "Boundary Scan" in the sources window.





From the main menu, choose Output -> Cable Setup... and select Communication Mode = Xilinx USB Cable. Click OK.






Right click in main window, and choose Initialize Chain. Three devices should be detected (xc3s500e, xcf04s, xc2c64). You will be asked to select configuration files for each one. Choose your .bit file for the first device. Skip the last two by clicking Bypass or Cancel.




Right click on the first device (xc3s500e) and choose Program... Another window will appear. You shouldn't need to change anything here, just click OK. Your design will be loaded onto the FPGA.




Congratulations! You're finished. If you want to, you can save your design onto the board's PROM so it's automatically loaded when the board is turned on. There's instructions on how to do this in the S3E Board User Guide, starting on page 31.