Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.3 (ISE) - M.70d Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx16
Project ID (random number) 95a37c67b93948e5a7fd9bf44d090e9d.4AEE126F0D5F45E281D7E07C29996105.1 Target Package: csg324
Registration ID 177724473_208900124_767 Target Speed: -3
Date Generated 2012-03-13T08:49:32 Tool Flow ISE
 
User Environment
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 930 @ 2.80GHz CPU Speed 2833 MHz
OS Name Microsoft OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 930 @ 2.80GHz CPU Speed 2833 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 23-bit adder=1
  • 3-bit adder=1
  • 4-bit adder=1
  • 5-bit adder=1
Comparators=9
  • 1-bit comparator not equal=1
  • 11-bit comparator greater=4
  • 11-bit comparator lessequal=2
  • 4-bit comparator lessequal=2
Counters=8
  • 10-bit up counter=1
  • 11-bit up counter=3
  • 15-bit up counter=1
  • 19-bit up counter=1
  • 4-bit up counter=1
  • 9-bit up counter=1
FSMs=2 Multiplexers=44
  • 1-bit 2-to-1 multiplexer=19
  • 16-bit 2-to-1 multiplexer=1
  • 23-bit 2-to-1 multiplexer=2
  • 3-bit 2-to-1 multiplexer=5
  • 4-bit 2-to-1 multiplexer=4
  • 5-bit 2-to-1 multiplexer=10
  • 8-bit 2-to-1 multiplexer=3
RAMs=7
  • 16x1-bit single-port distributed Read Only RAM=1
  • 16x2-bit single-port distributed Read Only RAM=1
  • 16x8-bit single-port distributed Read Only RAM=1
  • 32x6-bit single-port distributed Read Only RAM=1
  • 512x16-bit dual-port block RAM=1
  • 8x2-bit single-port distributed Read Only RAM=2
Registers=264
  • Flip-Flops=264
MiscellaneousStatistics
  • AGG_BONDED_IO=73
  • AGG_IO=73
  • AGG_LOCED_IO=73
  • AGG_SLICE=160
  • NUM_BONDED_IOB=73
  • NUM_BSFULL=254
  • NUM_BSLUTONLY=169
  • NUM_BSREGONLY=62
  • NUM_BSUSED=485
  • NUM_BUFG=6
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_DCM=1
  • NUM_DPRAM_O5ANDO6=8
  • NUM_IOB_FF=1
  • NUM_LOCED_IOB=73
  • NUM_LOGIC_O5ANDO6=96
  • NUM_LOGIC_O5ONLY=81
  • NUM_LOGIC_O6ONLY=205
  • NUM_LUT_RT_DRIVES_CARRY4=6
  • NUM_LUT_RT_DRIVES_FLOP=10
  • NUM_LUT_RT_EXO5=10
  • NUM_LUT_RT_EXO6=6
  • NUM_LUT_RT_O5=2
  • NUM_LUT_RT_O6=81
  • NUM_OLOGIC2=1
  • NUM_RAMB16BWER=1
  • NUM_RAMB8BWER=1
  • NUM_SLICEL=48
  • NUM_SLICEM=7
  • NUM_SLICEX=105
  • NUM_SLICE_CARRY4=40
  • NUM_SLICE_CONTROLSET=35
  • NUM_SLICE_CYINIT=628
  • NUM_SLICE_F7MUX=8
  • NUM_SLICE_FF=355
  • NUM_SLICE_UNUSEDCTRL=47
  • NUM_SPRAM_O5ANDO6=8
  • NUM_SPRAM_O6ONLY=8
  • NUM_SRL_O6ONLY=1
  • NUM_UNUSABLE_FF_BELS=100
NetStatistics
  • NumNets_Active=783
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=24
  • NumNodesOfType_Active_BOUNCEIN=111
  • NumNodesOfType_Active_BUFGOUT=6
  • NumNodesOfType_Active_BUFHINP2OUT=12
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=115
  • NumNodesOfType_Active_CLKPINFEED=32
  • NumNodesOfType_Active_CNTRLPIN=166
  • NumNodesOfType_Active_DOUBLE=943
  • NumNodesOfType_Active_GENERIC=132
  • NumNodesOfType_Active_GLOBAL=84
  • NumNodesOfType_Active_INPUT=122
  • NumNodesOfType_Active_IOBIN2OUT=103
  • NumNodesOfType_Active_IOBOUTPUT=104
  • NumNodesOfType_Active_LUTINPUT=1690
  • NumNodesOfType_Active_OUTBOUND=750
  • NumNodesOfType_Active_OUTPUT=710
  • NumNodesOfType_Active_PADINPUT=84
  • NumNodesOfType_Active_PADOUTPUT=20
  • NumNodesOfType_Active_PINBOUNCE=455
  • NumNodesOfType_Active_PINFEED=2058
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=3
  • NumNodesOfType_Active_QUAD=692
  • NumNodesOfType_Active_REGINPUT=131
  • NumNodesOfType_Active_SINGLE=1279
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=64
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_IOBIN2OUT=2
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=3
  • NumNodesOfType_Vcc_LUTINPUT=196
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINBOUNCE=1
  • NumNodesOfType_Vcc_PINFEED=200
SiteStatistics
  • BUFG-BUFGMUX=6
  • IOB-IOBM=38
  • IOB-IOBS=35
  • SLICEL-SLICEM=24
  • SLICEX-SLICEL=24
  • SLICEX-SLICEM=17
SiteSummary
  • BUFG=6
  • BUFG_BUFG=6
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=40
  • DCM=1
  • DCM_DCM=1
  • FF_SR=42
  • HARD0=10
  • IOB=73
  • IOB_IMUX=20
  • IOB_INBUF=20
  • IOB_OUTBUF=69
  • LUT5=189
  • LUT6=388
  • LUT_OR_MEM5=16
  • LUT_OR_MEM6=25
  • OLOGIC2=1
  • OLOGIC2_OUTFF=1
  • PAD=73
  • PULL_OR_KEEP1=2
  • RAMB16BWER=1
  • RAMB16BWER_RAMB16BWER=1
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=313
  • SELMUX2_1=8
  • SLICEL=48
  • SLICEM=7
  • SLICEX=105
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[5.0:1]
  • CLKIN_DIVIDE_BY_2=[TRUE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
FF_SR
  • CK=[CK:41] [CK_INV:1]
  • SRINIT=[SRINIT0:41] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:37] [SYNC:5]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:69]
  • SLEW=[SLOW:69]
  • SUSPEND=[3STATE:69]
LUT_OR_MEM5
  • CLK=[CLK:16] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:16]
  • RAMMODE=[SPRAM32:8] [DPRAM32:8]
LUT_OR_MEM6
  • CLK=[CLK:24] [CLK_INV:1]
  • LUT_OR_MEM=[RAM:25]
  • RAMMODE=[SPRAM32:8] [SPRAM64:8] [SRL16:1] [DPRAM32:8]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
  • CLK1=[CLK1:1] [CLK1_INV:0]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:1]
  • CK1=[CK1_INV:0] [CK1:1]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[DDR:1]
  • SRINIT_OQ=[0:1]
  • SRTYPE_OQ=[ASYNC:1]
PULL_OR_KEEP1
  • PULLTYPE=[PULLUP:2]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • CLKB=[CLKB_INV:0] [CLKB:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[18:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • ENB=[ENB_INV:0] [ENB:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEB=[REGCEB_INV:0] [REGCEB:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTB=[RSTB:1] [RSTB_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEA0=[WEA0:1] [WEA0_INV:0]
  • WEA1=[WEA1:1] [WEA1_INV:0]
  • WEA2=[WEA2:1] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:1]
  • WEB0=[WEB0:1] [WEB0_INV:0]
  • WEB1=[WEB1:1] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:1]
  • WEB3=[WEB3:1] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[18:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[TRUE:1]
  • EN_RSTRAM_B=[TRUE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
REG_SR
  • CK=[CK:301] [CK_INV:12]
  • LATCH_OR_FF=[FF:313]
  • SRINIT=[SRINIT0:302] [SRINIT1:11]
  • SYNC_ATTR=[ASYNC:282] [SYNC:31]
SLICEL
  • CLK=[CLK:35] [CLK_INV:0]
SLICEM
  • CLK=[CLK:6] [CLK_INV:1]
SLICEX
  • CLK=[CLK:68] [CLK_INV:3]
 
Pin Data
BUFG
  • I0=6
  • O=6
BUFG_BUFG
  • I0=6
  • O=6
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=27
  • CO0=1
  • CO3=28
  • CYINIT=13
  • DI0=38
  • DI1=35
  • DI2=29
  • DI3=28
  • O0=38
  • O1=36
  • O2=34
  • O3=28
  • S0=40
  • S1=37
  • S2=35
  • S3=29
DCM
  • CLK0=1
  • CLK180=1
  • CLK2X=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS1=1
  • STATUS2=1
DCM_DCM
  • CLK0=1
  • CLK180=1
  • CLK2X=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
  • STATUS1=1
  • STATUS2=1
FF_SR
  • CE=19
  • CK=42
  • D=42
  • Q=42
  • SR=28
HARD0
  • 0=10
IOB
  • I=20
  • O=69
  • PAD=73
  • T=16
IOB_IMUX
  • I=20
  • OUT=20
IOB_INBUF
  • OUT=20
  • PAD=20
IOB_OUTBUF
  • IN=69
  • OUT=69
  • TRI=16
LUT5
  • A1=48
  • A2=54
  • A3=45
  • A4=51
  • A5=81
  • O5=189
LUT6
  • A1=156
  • A2=206
  • A3=257
  • A4=339
  • A5=325
  • A6=378
  • O6=388
LUT_OR_MEM5
  • A1=16
  • A2=16
  • A3=16
  • A4=16
  • A5=16
  • CLK=16
  • DI1=16
  • O5=16
  • WA1=16
  • WA2=16
  • WA3=16
  • WA4=16
  • WA5=16
  • WE=16
LUT_OR_MEM6
  • A1=25
  • A2=25
  • A3=25
  • A4=25
  • A5=25
  • A6=25
  • CLK=25
  • DI1=8
  • DI2=17
  • O6=25
  • WA1=24
  • WA2=24
  • WA3=24
  • WA4=24
  • WA5=24
  • WA6=24
  • WE=25
OLOGIC2
  • CLK0=1
  • CLK1=1
  • D1=1
  • D2=1
  • OCE=1
  • OQ=1
  • SR=1
OLOGIC2_OUTFF
  • CE=1
  • CK0=1
  • CK1=1
  • D1=1
  • D2=1
  • Q=1
  • SR=1
PAD
  • PAD=73
PULL_OR_KEEP1
  • PAD=2
RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • DOPA0=1
  • DOPA1=1
  • DOPB0=1
  • DOPB1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB16BWER_RAMB16BWER
  • ADDRA0=1
  • ADDRA1=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA2=1
  • ADDRA3=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • ADDRB0=1
  • ADDRB1=1
  • ADDRB10=1
  • ADDRB11=1
  • ADDRB12=1
  • ADDRB13=1
  • ADDRB2=1
  • ADDRB3=1
  • ADDRB4=1
  • ADDRB5=1
  • ADDRB6=1
  • ADDRB7=1
  • ADDRB8=1
  • ADDRB9=1
  • CLKA=1
  • CLKB=1
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA16=1
  • DIA17=1
  • DIA18=1
  • DIA19=1
  • DIA2=1
  • DIA20=1
  • DIA21=1
  • DIA22=1
  • DIA23=1
  • DIA24=1
  • DIA25=1
  • DIA26=1
  • DIA27=1
  • DIA28=1
  • DIA29=1
  • DIA3=1
  • DIA30=1
  • DIA31=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPA2=1
  • DIPA3=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=1
  • DOB3=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • DOPA0=1
  • DOPA1=1
  • DOPB0=1
  • DOPB1=1
  • ENA=1
  • ENB=1
  • REGCEA=1
  • REGCEB=1
  • RSTA=1
  • RSTB=1
  • WEA0=1
  • WEA1=1
  • WEA2=1
  • WEA3=1
  • WEB0=1
  • WEB1=1
  • WEB2=1
  • WEB3=1
RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
REG_SR
  • CE=191
  • CK=313
  • D=313
  • Q=313
  • SR=261
SELMUX2_1
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
SLICEL
  • A=5
  • A1=10
  • A2=11
  • A3=12
  • A4=34
  • A5=30
  • A6=44
  • AMUX=12
  • AQ=30
  • AX=7
  • B=7
  • B1=15
  • B2=17
  • B3=17
  • B4=34
  • B5=32
  • B6=44
  • BMUX=14
  • BQ=27
  • BX=6
  • C=1
  • C1=16
  • C2=17
  • C3=19
  • C4=35
  • C5=31
  • C6=44
  • CE=19
  • CIN=27
  • CLK=35
  • CMUX=16
  • COUT=27
  • CQ=31
  • CX=13
  • D=2
  • D1=14
  • D2=15
  • D3=16
  • D4=30
  • D5=28
  • D6=39
  • DMUX=11
  • DQ=23
  • DX=4
  • SR=31
SLICEM
  • A=2
  • A1=6
  • A2=6
  • A3=6
  • A4=6
  • A5=6
  • A6=6
  • AI=4
  • AMUX=4
  • AQ=5
  • AX=5
  • B=2
  • B1=6
  • B2=6
  • B3=6
  • B4=6
  • B5=6
  • B6=6
  • BI=4
  • BMUX=4
  • BQ=5
  • BX=7
  • C=2
  • C1=6
  • C2=6
  • C3=6
  • C4=6
  • C5=6
  • C6=6
  • CE=7
  • CI=4
  • CLK=7
  • CMUX=4
  • CQ=5
  • CX=5
  • D=2
  • D1=7
  • D2=7
  • D3=7
  • D4=7
  • D5=7
  • D6=7
  • DI=5
  • DMUX=4
  • DQ=5
  • DX=6
SLICEX
  • A=37
  • A1=42
  • A2=53
  • A3=62
  • A4=69
  • A5=68
  • A6=66
  • AMUX=19
  • AQ=55
  • AX=22
  • B=33
  • B1=32
  • B2=41
  • B3=48
  • B4=52
  • B5=56
  • B6=54
  • BMUX=13
  • BQ=44
  • BX=22
  • C=26
  • C1=31
  • C2=40
  • C3=44
  • C4=44
  • C5=46
  • C6=44
  • CE=44
  • CLK=71
  • CMUX=14
  • CQ=42
  • CX=24
  • D=26
  • D1=31
  • D2=37
  • D3=43
  • D4=44
  • D5=46
  • D6=43
  • DMUX=21
  • DQ=41
  • DX=23
  • SR=63
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx16-csg324-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
bitgen 206 206 0 0 0 0 0
bitinit 8 8 0 0 0 0 0
compxlib 1 1 0 0 0 0 0
elfcheck 2 2 0 0 0 0 0
libgen 12 11 0 0 0 0 0
map 208 206 0 0 0 0 0
netgen 4 4 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngcbuild 69 69 0 0 0 0 0
ngdbuild 226 226 0 0 0 0 0
par 206 206 0 0 0 0 0
platgen 10 10 0 0 0 0 0
psf2Edward 15 15 0 0 0 0 0
trce 200 200 0 0 0 0 0
xdsgen 6 6 0 0 0 0 0
xps 16 13 0 0 0 0 0
xst 435 411 0 0 0 0 0
 
Help Statistics
Search words with results
stdin ( 1 )
Help files
/doc/usenglish/platform_studio/ps_c_dbg_debugging_mb_sw_overview.htm ( 1 ) /doc/usenglish/platform_studio/ps_c_dbg_debugging_sw_multiprocessor.htm ( 1 )
/doc/usenglish/platform_studio/ps_c_hdw_generating_the_hardware_platform.htm ( 1 ) /doc/usenglish/platform_studio/ps_c_hdw_impl_hw_platform.htm ( 2 )
/doc/usenglish/platform_studio/ps_d_uart.htm ( 3 ) /doc/usenglish/platform_studio/ps_d_ucf.htm ( 1 )
/doc/usenglish/platform_studio/ps_p_dbg_debugging_sw_multi_starting_stdinout_terminal_in_xmd.htm ( 1 ) /doc/usenglish/platform_studio/ps_p_dbg_sw_mb_starting_stdin_out_terminal_xmd.htm ( 3 )
/doc/usenglish/platform_studio/ps_p_dbg_sw_mb_starting_xmd_connecting_to_mb_processor.htm ( 1 ) /doc/usenglish/platform_studio/ps_p_dbg_sw_ppc_starting_stdin_out_terminal_xmd.htm ( 2 )
/doc/usenglish/platform_studio/ps_p_hdw_setting_up_your_ucf.htm ( 1 ) /doc/usenglish/platform_studio/ps_r_gst_project_files.htm ( 1 )
/doc/usenglish/platform_studio/ps_r_gst_whatsnew.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-03-13T08:47:02
PROP_intWbtProjectID=4AEE126F0D5F45E281D7E07C29996105 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx16 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=csg324 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=11
FILE_VHDL=1
 
Core Statistics
Core Type=clk_wiz_v1_7
clkin1_period=10.0 clkin2_period=10.0 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=5 primtype_sel=DCM_SP
use_clk_valid=true use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=false use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=5 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=51
NGDBUILD_NUM_FDC=63 NGDBUILD_NUM_FDCE=178 NGDBUILD_NUM_FDE=9 NGDBUILD_NUM_FDP=2
NGDBUILD_NUM_FDPE=10 NGDBUILD_NUM_FDR=24 NGDBUILD_NUM_FDRE=14 NGDBUILD_NUM_FD_1=8
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=12
NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT1=91 NGDBUILD_NUM_LUT2=11 NGDBUILD_NUM_LUT3=27
NGDBUILD_NUM_LUT4=58 NGDBUILD_NUM_LUT5=46 NGDBUILD_NUM_LUT6=128 NGDBUILD_NUM_LUT6_2=50
NGDBUILD_NUM_MUXCY=130 NGDBUILD_NUM_MUXF7=8 NGDBUILD_NUM_OBUF=53 NGDBUILD_NUM_ODDR2=1
NGDBUILD_NUM_RAM32M=4 NGDBUILD_NUM_RAM64M=2 NGDBUILD_NUM_RAMB16BWER=1 NGDBUILD_NUM_RAMB8BWER=1
NGDBUILD_NUM_SRLC16E=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=136
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=6 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=51 NGDBUILD_NUM_FDC=63
NGDBUILD_NUM_FDCE=178 NGDBUILD_NUM_FDE=9 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=10
NGDBUILD_NUM_FDR=24 NGDBUILD_NUM_FDRE=14 NGDBUILD_NUM_FD_1=8 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=18 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=12 NGDBUILD_NUM_LUT1=91
NGDBUILD_NUM_LUT2=11 NGDBUILD_NUM_LUT3=27 NGDBUILD_NUM_LUT4=58 NGDBUILD_NUM_LUT5=46
NGDBUILD_NUM_LUT6=128 NGDBUILD_NUM_LUT6_2=50 NGDBUILD_NUM_MUXCY=130 NGDBUILD_NUM_MUXF7=8
NGDBUILD_NUM_OBUF=53 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_PULLUP=2
NGDBUILD_NUM_RAM32M=4 NGDBUILD_NUM_RAM64M=2 NGDBUILD_NUM_RAMB16BWER=1 NGDBUILD_NUM_RAMB8BWER=1
NGDBUILD_NUM_SRLC16E=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=136