psram_app Project Status (03/13/2012 - 08:49:43)
Project File: psram_app.xise Parser Errors: No Errors
Module Name: psram_app Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
No Errors
Product Version:ISE 12.3
  • Warnings:
6 Warnings (6 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 355 18,224 1%  
    Number used as Flip Flops 355      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 423 9,112 4%  
    Number used as logic 382 9,112 4%  
        Number using O6 output only 205      
        Number using O5 output only 81      
        Number using O5 and O6 96      
        Number used as ROM 0      
    Number used as Memory 25 2,176 1%  
        Number used as Dual Port RAM 8      
            Number using O6 output only 0      
            Number using O5 output only 0      
            Number using O5 and O6 8      
        Number used as Single Port RAM 16      
            Number using O6 output only 8      
            Number using O5 output only 0      
            Number using O5 and O6 8      
        Number used as Shift Register 1      
            Number using O6 output only 1      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 16      
        Number with same-slice register load 10      
        Number with same-slice carry load 6      
        Number with other load 0      
Number of occupied Slices 160 2,278 7%  
Number of LUT Flip Flop pairs used 485      
    Number with an unused Flip Flop 169 485 34%  
    Number with an unused LUT 62 485 12%  
    Number of fully used LUT-FF pairs 254 485 52%  
    Number of unique control sets 35      
    Number of slice register sites lost
        to control set restrictions
100 18,224 1%  
Number of bonded IOBs 73 232 31%  
    Number of LOCed IOBs 73 73 100%  
    IOB Flip Flops 1      
Number of RAMB16BWERs 1 32 3%  
Number of RAMB8BWERs 1 64 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 6 16 37%  
    Number used as BUFGs 6      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 1 248 1%  
    Number used as OLOGIC2s 1      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.63      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentT 13. märts 08:48:40 201203 Warnings (3 new)12 Infos (12 new)
Translation ReportCurrentT 13. märts 08:48:44 201203 Warnings (3 new)0
Map ReportCurrentT 13. märts 08:49:05 2012007 Infos (7 new)
Place and Route ReportCurrentT 13. märts 08:49:17 2012004 Infos (4 new)
Power Report     
Post-PAR Static Timing ReportCurrentT 13. märts 08:49:22 2012003 Infos (3 new)
Bitgen ReportCurrentT 13. märts 08:49:32 2012001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentT 13. märts 08:49:32 2012
WebTalk Log FileCurrentT 13. märts 08:49:43 2012

Date Generated: 03/13/2012 - 08:49:43