v64 setup version 0 1 1;

/* This msa file was converted from the tester setup used in */
/* the 74ls299 example presented in the lecture notes	     */

/* config section */

resolution = 500ps;
dev_supply_voltage	=	5.00v;
dev_supply_current	=	1.00a;

term_supply_voltage	=	3.00v;

force_high_family_v1	=	2.40v;
force_low_family_v1	=	0.50v;
compare_family_v1	=	1.40v;

force_high_family_v2	=	4.50v;
force_low_family_v2	=	0.50v;
compare_family_v2	=	2.50v;

sector_logic_family	=	{
	v1, v1, v1, v1,  ,  ,  ,  , v1, v1, v1, v1,  ,  ,  , 
};


/* group section */

group "clr" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 0a;
	signal "clr~" {
		dut = "U_0";
		sector = 0h1;
		channel = 0hf;
	}
}

group "sel" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 0a;
	signal "s1" {
		dut = "U_1";
		sector = 0h1;
		channel = 0hd;
	}
	signal "s0" {
		dut = "U_2";
		sector = 0h1;
		channel = 0hc;
	}
}

group "data" {
	radix = bin;
	force_fmt = ri;
	compare_fmt = edge_t;
	phase = 0c;
	signal "d0" {
		dut = "U_10";
		sector = 0h2;
		channel = 0h4;
	}
	signal "d1" {
		dut = "U_9";
		sector = 0h2;
		channel = 0h5;
	}
	signal "d2" {
		dut = "U_8";
		sector = 0h2;
		channel = 0h6;
	}
	signal "d3" {
		dut = "U_7";
		sector = 0h2;
		channel = 0h7;
	}
	signal "d4" {
		dut = "U_6";
		sector = 0h2;
		channel = 0h8;
	}
	signal "d5" {
		dut = "U_5";
		sector = 0h2;
		channel = 0h9;
	}
	signal "d6" {
		dut = "U_4";
		sector = 0h2;
		channel = 0ha;
	}
	signal "d7" {
		dut = "U_3";
		sector = 0h2;
		channel = 0hb;
	}
}

group "slr" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 0a;
	signal "sl" {
		dut = "U_11";
		sector = 0h2;
		channel = 0h1;
	}
	signal "sr" {
		dut = "U_12";
		sector = 0h2;
		channel = 0h0;
	}
}

group "clk" {
	radix = bin;
	force_fmt = r0;
	compare_fmt = edge_t;
	phase = 0b;
	signal "clk" {
		dut = "U_13";
		sector = 0h1;
		channel = 0he;
	}
}

group "en" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 0a;
	signal "en1~" {
		dut = "U_14";
		sector = 0h1;
		channel = 0ha;
	}
	signal "en2~" {
		dut = "U_15";
		sector = 0h1;
		channel = 0hb;
	}
}

group "q" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 0a;
	signal "q0" {
		dut = "U_16";
		sector = 0h2;
		channel = 0h2;
	}
	signal "q7" {
		dut = "U_17";
		sector = 0h2;
		channel = 0h3;
	}
}

/* template section */

template "clear" {
	cycle = 200ns;
	phase 0a {delay = 0ns; width = 100ns;}
	phase 0b {delay = 40ns; width = 100ns;}
	phase 0c {delay = 20ns; width = 80ns;}
	group "clr" {
		function = force;
	}
	group "sel" {
		function = force;
	}
	group "data" {
		function = compare;
	}
	group "slr" {
		function = force;
	}
	group "clk" {
		function = force;
	}
	group "en" {
		function = force;
	}
	group "q" {
		function = compare;
	}
}

template "shift" {
	cycle = 200ns;
	phase 0a {delay = 0ns; width = 100ns;}
	phase 0b {delay = 40ns; width = 100ns;}
	phase 0c {delay = 20ns; width = 80ns;}
	group "clr" {
		function = force;
	}
	group "sel" {
		function = force;
	}
	group "data" {
		function = compare;
	}
	group "slr" {
		function = force;
	}
	group "clk" {
		function = force;
	}
	group "en" {
		function = force;
	}
	group "q" {
		function = compare;
	}
}

template "load" {
	cycle = 200ns;
	phase 0a {delay = 0ns; width = 100ns;}
	phase 0b {delay = 40ns; width = 100ns;}
	phase 0c {delay = 20ns; width = 80ns;}
	group "clr" {
		function = force;
	}
	group "sel" {
		function = force;
	}
	group "data" {
		function = force;
	}
	group "slr" {
		function = force;
	}
	group "clk" {
		function = force;
	}
	group "en" {
		function = force;
	}
	group "q" {
		function = compare;
	}
}

/* schmoo define section */

schmoo_var_x = not_selected;
schmoo_var_y = not_selected;

pmu_test "PMU_test_0" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_1" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_2" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_3" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_4" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_schedule {
}

/* macro section */

macro macro_0() {
	*	"";
}

/* define format info */


define_format {
}
/* pattern section */

pattern 
	*	"Simple test of the 299 shifter";
	"clear"	0 00 00000000 00 1 00 00;
	"shift"	1 00 00000000 00 1 00 00;
	"shift"	1 00 00000000 11 1 00 00;
	"shift"	1 01 10000000 11 1 00 10;
	"shift"	1 01 11000000 11 1 00 10;
	"shift"	1 10 10000001 11 1 00 11;
	"load"	1 11 01010101 00 1 00 01;
	"shift"	1 00 01010101 00 1 00 01;
	"shift"	1 10 10101010 00 1 00 10;
	"shift"	1 10 01010100 00 1 00 00;
	"shift"	1 10 10101001 10 1 00 11;
	"shift"	1 10 01010011 10 1 00 01;