v64 setup version 0 1 1;

/* config section */

resolution = 500ps;
dev_supply_voltage	=	5.00v;
dev_supply_current	=	1.00a;

term_supply_voltage	=	3.00v;

force_high_family_v1	=	5.00v;
force_low_family_v1	=	0.50v;
compare_family_v1	=	1.40v;

force_high_family_v2	=	4.50v;
force_low_family_v2	=	0.50v;
compare_family_v2	=	2.50v;

sector_logic_family	=	{
	v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1,  ,  ,  , 
};


/* group section */

group "OUT" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 1b;
	phase = 2a;
	signal "OUT9" {
		dut = "75";
		sector = 0h7;
		channel = 0h8;
	}
	signal "OUT8" {
		dut = "73";
		sector = 0h7;
		channel = 0h0;
	}
	signal "OUT7" {
		dut = "72";
		sector = 0h6;
		channel = 0h6;
	}
	signal "OUT6" {
		dut = "71";
		sector = 0h7;
		channel = 0h1;
	}
	signal "OUT5" {
		dut = "70";
		sector = 0h7;
		channel = 0h9;
	}
	signal "OUT4" {
		dut = "69";
		sector = 0h6;
		channel = 0h7;
	}
	signal "OUT3" {
		dut = "58";
		sector = 0h7;
		channel = 0hf;
	}
	signal "OUT2" {
		dut = "56";
		sector = 0h8;
		channel = 0h4;
	}
	signal "OUT1" {
		dut = "55";
		sector = 0h8;
		channel = 0h5;
	}
	signal "OUT0" {
		dut = "54";
		sector = 0h8;
		channel = 0h3;
	}
	signal "ADDSUBOF" {
		dut = "52";
		sector = 0h8;
		channel = 0h8;
	}
	signal "NEG" {
		dut = "51";
		sector = 0h8;
		channel = 0hf;
	}
	signal "MULTOF" {
		dut = "37";
		sector = 0ha;
		channel = 0ha;
	}
	signal "DONE" {
		dut = "35";
		sector = 0h9;
		channel = 0hf;
	}
	signal "DIVZERO" {
		dut = "36";
		sector = 0h9;
		channel = 0h6;
	}
}

group "OPCODE" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 2a;
	signal "OP3" {
		dut = "29";
		sector = 0h9;
		channel = 0hd;
	}
	signal "OP2" {
		dut = "30";
		sector = 0ha;
		channel = 0h8;
	}
	signal "OP1" {
		dut = "31";
		sector = 0h9;
		channel = 0h4;
	}
	signal "OP0" {
		dut = "32";
		sector = 0h9;
		channel = 0h5;
	}
}

group "RESET" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 2a;
	signal "RESET" {
		dut = "34";
		sector = 0ha;
		channel = 0h9;
	}
}

group "BEGIN" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 1b;
	signal "BEGIN" {
		dut = "6";
		sector = 0h7;
		channel = 0hc;
	}
}

group "CLOCK" {
	radix = bin;
	force_fmt = r0;
	compare_fmt = edge_t;
	phase = 1a;
	signal "CLK" {
		dut = "79";
		sector = 0h6;
		channel = 0h3;
	}
}

group "INPUT" {
	radix = bin;
	force_fmt = dnrz_l;
	compare_fmt = edge_t;
	phase = 2a;
	signal "IN9" {
		dut = "8";
		sector = 0h8;
		channel = 0h1;
	}
	signal "IN8" {
		dut = "9";
		sector = 0h8;
		channel = 0h0;
	}
	signal "IN7" {
		dut = "10";
		sector = 0h8;
		channel = 0h2;
	}
	signal "IN6" {
		dut = "11";
		sector = 0h8;
		channel = 0h7;
	}
	signal "IN5" {
		dut = "12";
		sector = 0h8;
		channel = 0h6;
	}
	signal "IN4" {
		dut = "13";
		sector = 0h8;
		channel = 0ha;
	}
	signal "IN3" {
		dut = "14";
		sector = 0h8;
		channel = 0hb;
	}
	signal "IN2" {
		dut = "15";
		sector = 0h8;
		channel = 0hc;
	}
	signal "IN1" {
		dut = "27";
		sector = 0ha;
		channel = 0h7;
	}
	signal "IN0" {
		dut = "28";
		sector = 0h9;
		channel = 0he;
	}
}

/* template section */

template "TEMP" {
	cycle = 268ns;
	phase 2a {delay = 25ns; width = 200ns;}
	phase 2b {delay = 250ns; width = 8ns;}
	phase 1a {delay = 50ns; width = 100ns;}
	phase 1b {delay = 25ns; width = 200ns;}
	group "OUT" {
		function = compare;
	}
	group "OPCODE" {
		function = force;
	}
	group "RESET" {
		function = force;
	}
	group "BEGIN" {
		function = force;
	}
	group "CLOCK" {
		function = force;
	}
	group "INPUT" {
		function = force;
	}
}

/* schmoo define section */

schmoo_var_x = not_selected;
schmoo_var_y = not_selected;

pmu_test "PMU_test_0" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_1" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_2" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_3" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_test "PMU_test_4" {
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
	no_test;
}


pmu_schedule {
}

/* macro section */

macro CHECKER() {
	*	"";
}

/* define format info */


define_format {
}
/* pattern section */

pattern 
	*	"RESET TEST";
	"TEMP"	000000000000000 0000 0 0 1 0000000000;
	"TEMP"	000000000000000 0000 0 0 1 0000000000;
	*	"LOAD POSITIVE #";
	"TEMP"	000000000000000 0010 1 1 1 0010001000;
	"TEMP"	000000000000000 0010 1 0 1 0010001000;
	"TEMP"	000000000000000 0010 1 0 1 0010001000;
	"TEMP"	001000100000010 0010 1 0 1 0010001000;
	"TEMP"	001000100000010 0010 1 0 1 1111111111;
	"TEMP"	001000100000000 0010 1 0 1 1111111111;
	"TEMP"	001000100000000 0010 1 0 1 1111111111;
	"TEMP"	001000100000000 0010 1 0 1 1111111111;
	*	"LOAD NEGATIVE #";
	"TEMP"	001000100000000 0010 1 1 1 1111111111;
	"TEMP"	001000100000000 0010 1 0 1 1111111111;
	"TEMP"	001000100000000 0010 1 0 1 1111111111;
	"TEMP"	000000000101010 0010 1 0 1 0000000000;
	"TEMP"	000000000101010 0010 1 0 1 0000000000;
	"TEMP"	000000000101000 1110 1 0 1 0000001111;
	*	"ADD NEGATIVE+POSITIVE";
	"TEMP"	000000000101000 1110 1 1 1 0000001111;
	"TEMP"	000000000101000 1110 1 0 1 0000001111;
	"TEMP"	000000000101000 1110 1 0 1 0000001111;
	"TEMP"	000000111000010 1110 1 0 1 0000001111;
	"TEMP"	000000111000010 1110 1 0 1 0000001111;
	"TEMP"	000000111000000 1110 1 0 1 1001110000;
	*	"ADD POSITIVE+NEGATIVE";
	"TEMP"	000000111000000 1110 1 1 1 1001110000;
	"TEMP"	000000111000000 1110 1 0 1 1001110000;
	"TEMP"	000000111000000 1110 1 0 1 1001110000;
	"TEMP"	011000001001010 1110 1 0 1 1111111111;
	"TEMP"	011000001001010 1110 1 0 1 1111111111;
	"TEMP"	011000001001000 1110 1 0 1 1000111111;
	*	"ADD NEGATIVE+NEGATIVE WITH OVERFLOW";
	"TEMP"	011000001001000 1110 1 1 1 1000111111;
	"TEMP"	011000001001000 1110 1 0 1 1000111111;
	"TEMP"	011000001001000 1110 1 0 1 1000111111;
	"TEMP"	001011110100010 1110 1 0 1 1000111111;
	*	"MISSED OVERFLOW WITH TWO NEGATIVES";
	*	"RESET AGAIN";
	"TEMP"	000000000000000 0000 0 0 1 0000000000;
	"TEMP"	000000000000000 0010 1 1 1 0111111000;
	"TEMP"	000000000000000 0010 1 0 1 0111111000;
	"TEMP"	000000000000000 0010 1 0 1 0111111000;
	"TEMP"	011111100000010 0010 1 0 1 0111111000;
	"TEMP"	011111100000010 0010 1 0 1 0111111000;
	"TEMP"	011111100000000 0010 1 0 1 0111111000;
	*	"ADD POSITIVE+POSITIVE FOR OVERFLOW";
	"TEMP"	011111100000000 1110 1 1 1 0111000000;
	"TEMP"	011111100000000 1110 1 0 1 0111000000;
	"TEMP"	011111100000000 1110 1 0 1 0111000000;
	"TEMP"	000100100001010 1110 1 0 1 0111000000;
	"TEMP"	000100100001010 1110 1 0 1 0111000000;
	"TEMP"	000100100001000 1110 1 0 1 0111000000;
	*	"OVERFLOW BIT DOES NOT WORK";
	*	"RESET";
	"TEMP"	000000000000000 0000 0 0 1 0000000000;
	*	"LOAD";
	"TEMP"	000000000000000 0010 1 1 1 0001100110;
	"TEMP"	000000000000000 0010 1 0 1 0001100110;
	"TEMP"	000000000000000 0010 1 0 1 0001100110;
	"TEMP"	000110011000010 0010 1 0 1 0001100110;
	"TEMP"	000110011000010 0010 1 0 1 0001100110;
	"TEMP"	000110011000000 1110 1 0 1 0001100110;
	*	"ADD POS+POS NO OVERFLOW";
	"TEMP"	000110011000000 1110 1 1 1 0001100110;
	"TEMP"	000110011000000 1110 1 0 1 0001100110;
	"TEMP"	000110011000000 1110 1 0 1 0001100110;
	"TEMP"	001100110000010 1110 1 0 1 0001100110;
	"TEMP"	001100110000010 1110 1 0 1 0001100110;
	*	"RESULT VERIFIED";
	*	"ADD POS+POS AGAIN NO OVERFLOW";
	"TEMP"	001100110000000 1110 1 0 1 0001100110;
	"TEMP"	001100110000000 1110 1 1 1 0001100110;
	"TEMP"	001100110000000 1110 1 0 1 0001100110;
	"TEMP"	001100110000000 1110 1 0 1 0001100110;
	"TEMP"	010011001000010 1110 1 0 1 0001100110;
	"TEMP"	010011001000010 1110 1 0 1 0001100110;
	"TEMP"	010011001000000 1110 1 0 1 0001100110;
	*	"RESULT VERIFIED";
	*	"ADD POS+NEG NO OVERFLOW";
	"TEMP"	010011001000000 1110 1 1 1 1001100110;
	"TEMP"	010011001000000 1110 1 0 1 1001100110;
	"TEMP"	010011001000000 1110 1 0 1 1001100110;
	"TEMP"	000110100001010 1110 1 0 1 1001100110;
	"TEMP"	000110100001010 1110 1 0 1 1001100110;
	"TEMP"	000110100001000 1110 1 0 1 1001100110;
	*	"OUTPUT VERIFIED";
	*	"ADD NEG+NEG NO OVERFLOW";
	"TEMP"	000110100001000 1110 1 1 1 1111100110;
	"TEMP"	000110100001000 1110 1 0 1 1111100110;
	"TEMP"	000110100001000 1110 1 0 1 1111100110;
	"TEMP"	001000001001010 1110 1 0 1 1111100110;
	"TEMP"	001000001001010 1110 1 0 1 1111100110;
	"TEMP"	001000001001000 1110 1 0 1 1111100110;
	*	"RESULT VERIFIED";
	*	"ADD NEG + NEG NO OVERFLOW";
	"TEMP"	001000001001000 1110 1 1 1 1111111110;
	"TEMP"	001000001001000 1110 1 0 1 1111111110;
	"TEMP"	001000001001000 1110 1 0 1 1111111110;
	"TEMP"	001000010001010 1110 1 0 1 1111111110;
	"TEMP"	001000010001010 1110 1 0 1 1111111110;
	"TEMP"	001000010001000 1110 1 0 1 1111111110;
	"TEMP"	001000010001000 1110 1 0 1 1111111110;
	*	"OUTPUT VERIFIED";
	*	"ADD NEG+POS NO OVERFLOW";
	"TEMP"	001000010001000 1110 1 1 1 0111111110;
	"TEMP"	001000010001000 1110 1 0 1 0111111110;
	"TEMP"	001000010001000 1110 1 0 1 0111111110;
	"TEMP"	010111101000010 1110 1 0 1 0111111110;
	"TEMP"	010111101000010 1110 1 0 1 0111111110;
	"TEMP"	010111101000000 1110 1 0 1 0111111110;
	*	"RESULT VERIFIED";
	*	"SUB POS-POS NO OVERFLOW";
	"TEMP"	010111101000000 1111 1 1 1 0101110100;
	"TEMP"	010111101000000 1111 1 0 1 0101110100;
	"TEMP"	010111101000000 1111 1 0 1 0101110100;
	"TEMP"	000000011000010 1111 1 0 1 0101110100;
	"TEMP"	000000011000010 1111 1 0 1 0101110100;
	"TEMP"	000000011000000 1111 1 0 1 0101110100;
	*	"VERIFIED";
	*	"SUB POS-POS";
	"TEMP"	000000011000000 1111 1 1 1 0000000011;
	"TEMP"	000000011000000 1111 1 0 1 0000000011;
	"TEMP"	000000011000000 1111 1 0 1 0000000011;
	"TEMP"	000000001100010 1111 1 0 1 0000000011;
	"TEMP"	000000001100010 1111 1 0 1 0000000011;
	"TEMP"	000000001100000 1111 1 0 1 0000000011;
	*	"VERIFIED";
	*	"SUB POS-NEG";
	"TEMP"	000000001100000 1111 1 1 1 1111100011;
	"TEMP"	000000001100000 1111 1 0 1 1111100011;
	"TEMP"	000000001100000 1111 1 0 1 1111100011;
	"TEMP"	000010000000010 1111 1 0 1 1111100011;
	"TEMP"	000010000000010 1111 1 0 1 1111100011;
	"TEMP"	000010000000000 1111 1 0 1 1111100011;
	*	"VERIFIED";
	*	"SUB POS-NEG";
	"TEMP"	000010000000000 1111 1 1 1 1111000011;
	"TEMP"	000010000000000 1111 1 0 1 1111000011;
	"TEMP"	000010000000000 1111 1 0 1 1111000011;
	"TEMP"	000101110100010 1111 1 0 1 1111000011;
	"TEMP"	000101110100010 1111 1 0 1 1111000011;
	"TEMP"	000101110100000 1111 1 0 1 1111000011;
	*	"VERIFIED";
	*	"SUB POS-POS";
	"TEMP"	000101110100000 1111 1 1 1 0111111111;
	"TEMP"	000101110100000 1111 1 0 1 0111111111;
	"TEMP"	000101110100000 1111 1 0 1 0111111111;
	"TEMP"	011010001001010 1111 1 0 1 0111111111;
	"TEMP"	011010001001010 1111 1 0 1 0111111111;
	"TEMP"	011010001001000 1111 1 0 1 0111111111;
	*	"VERIFIED";
	*	"SUB NEG-POS";
	"TEMP"	011010001001000 1111 1 1 1 0000000011;
	"TEMP"	011010001001000 1111 1 0 1 0000000011;
	"TEMP"	011010001001000 1111 1 0 1 0000000011;
	"TEMP"	011010010101010 1111 1 0 1 0000000011;
	"TEMP"	011010010101010 1111 1 0 1 0000000011;
	"TEMP"	011010010101000 1111 1 0 1 0000000011;
	*	"VERIFIED";
	*	"SUB NEG-POS";
	"TEMP"	011010010101000 1111 1 1 1 0000001111;
	"TEMP"	011010010101000 1111 1 0 1 0000001111;
	"TEMP"	011010010101000 1111 1 0 1 0000001111;
	"TEMP"	011011010001010 1111 1 0 1 0000001111;
	"TEMP"	011011010001010 1111 1 0 1 0000001111;
	"TEMP"	011011010001000 1111 1 0 1 0000001111;
	*	"VERIFIED";
	*	"SUB NEG-NEG";
	"TEMP"	011011010001000 1111 1 1 1 1111001111;
	"TEMP"	011011010001000 1111 1 0 1 1111001111;
	"TEMP"	011011010001000 1111 1 0 1 1111001111;
	"TEMP"	011000001101010 1111 1 0 1 1111001111;
	"TEMP"	011000001101010 1111 1 0 1 1111001111;
	"TEMP"	011000001101000 1111 1 0 1 1111001111;
	*	"VERIFIED";
	*	"SUB NEG-NEG";
	"TEMP"	011000001101000 1111 1 1 1 1111001101;
	"TEMP"	011000001101000 1111 1 0 1 1111001101;
	"TEMP"	011000001101000 1111 1 0 1 1111001101;
	"TEMP"	010101000001010 1111 1 0 1 1111001101;
	"TEMP"	010101000001010 1111 1 0 1 1111001101;
	"TEMP"	010101000001000 1111 1 0 1 1111001101;
	*	"VERIFIED";
	*	"MULT NEG*NEG OVERFLOW";
	"TEMP"	010101000001000 1100 1 1 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001000 1100 1 0 1 1111001101;
	"TEMP"	010101000001100 1100 1 0 1 1111001101;
	"TEMP"	010101000001100 1100 1 0 1 1111001101;
	"TEMP"	010101000001100 1100 1 0 1 1111001101;
	"TEMP"	000100000001110 1100 1 0 1 1111001101;
	"TEMP"	000100000001110 1100 1 0 1 1111001101;
	"TEMP"	000100000001100 1100 1 0