PAD-PIN-TESTER CHANNEL MAP FOR CS/EE 5710/6710 DUT CARD This map is for the "new" card with the orange wires on the back, and is usable on both the LV514 and LV512. Pad locations are taken from MOSIS bonding diagram PGA locations are taken from 84pin PGA bonding diagram Tester channels 8.9,A,B,0 are used. The notation is sector.channel Vdd and GND connections are as per 5710 standard pad frame and are connected directly on the DUT card - no tester mapping is required for VDD and GND (see note below). Note that if you're testing an old chip that uses all 6 VDD/GND connections from the old test frames, those chips would have VDD on pin 33 (L6), and GND on pin 74 (C6). In that case you must define those pins as "mask" in your template so that they are not driven by the tester. TESTER SIGNAL PAD PGA sec.chn NAME (no spaces) --------------------------------- 1 B02 8.0 2 C02 8.1 3 B01 8.2 4 C01 8.3 5 D02 8.4 6 D01 8.5 7 F02 GND GND 8 E02 8.6 9 E01 8.7 10 E03 8.8 11 F03 8.9 12 F01 8.A 13 G01 8.B 14 G02 8.C 15 G03 8.D 16 H01 VDD VDD 17 H02 8.E 18 J01 8.F 19 K01 9.0 20 J02 9.1 21 L01 9.2 22 K02 9.3 23 K03 9.4 24 L02 9.5 25 L03 9.6 26 K04 9.7 27 L04 9.8 28 K06 9.9 29 K05 9.A 30 L05 9.B 31 J05 9.C 32 J06 9.D 33 L06 9.E 34 L07 9.F 35 K07 A.0 36 J07 A.1 37 L08 A.2 38 K08 A.3 39 L09 A.4 40 L10 A.5 41 K09 A.6 42 L11 A.7 43 K10 A.8 44 J10 A.9 45 K11 A.A 46 J11 A.B 47 H10 A.C 48 H11 GND GND 49 G09 A.D 50 G10 A.E 51 G11 A.F 52 F10 B.0 53 F09 B.1 54 E09 B.2 55 E11 B.3 56 E10 B.4 57 F11 VDD VDD 58 D11 B.5 59 D10 B.6 60 C11 B.7 61 B11 B.8 62 C10 B.9 63 A11 B.A 64 B10 B.B 65 B09 B.C 66 A10 B.D 67 A09 B.E 68 B08 B.F 69 A08 0.0 70 C07 0.1 71 B07 0.2 72 A07 0.3 73 B06 0.4 74 C06 0.5 75 C05 0.6 76 A05 0.7 77 B05 0.8 78 A06 0.9 79 A04 0.A 80 B04 0.B 81 A03 0.C 82 A02 0.D 83 B03 0.E 84 A01 0.F