Log file Generated by mig version 1.5 at Fri Jul 7 12:43:02 2006 Reading design libraries of xc3s500e-fg320... successful ! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2...successful! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/par...successful! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs ...successful! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/synth ...successful! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/sim ...successful! Creating the directory C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl ...successful! /*******************************************************/ /* Controller 0 */ /*******************************************************/ Cloning Data bits ...successful! Cloning Strobe bits ...successful! Cloning Mask bits ...successful! Removing unwanted signals names from MT46V32M16P-5B... successful! Copying all the files from docs ... copying c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/docs/DDR SDRAM/768c.pdf to C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs ...successful! copying c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/docs/DDR SDRAM/xapp701.pdf to C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs ...successful! copying c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/docs/DDR SDRAM/xapp709.pdf to C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs ...successful! copying c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/docs/DDR SDRAM/XAPP768c.pdf to C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs ...successful! ...successful! Reading the file c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/dlib/spartan3/DDR SDRAM/verilog/filenames.xml...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_cal_top.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_clk_dcm.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_cmd_fsm_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_path_rst.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_ddr1_test_bench_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_dqs_delay.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_fifo_0_wr_en_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_fifo_1_wr_en_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_glbl.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_infrastructure.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_infrastructure_top.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_parameters_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_rd_gray_cntr.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_s3_ddr_iob.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_s3_dqs_iob.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_wr_gray_cntr.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_parameters_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_cmp_data_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_cal_ctl_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_mybufg_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_tap_dly_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_controller_iobs_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_addr_gen_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_path_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_path_iobs_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_read_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_RAM8D_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_read_controller_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_data_write_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_ddr1_dm_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_main_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_top_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_infrastructure_iobs_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_iobs_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_lfsr32_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_controller_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_ucf_constraints_0.v ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/synth/xst_vlog_bl2cl2_script_pre_0.tcl ...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_sdc_constraints_0.v ...successful! Writing to the fileC:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/par/xst_vlog_bl2cl2.ucfChecking for synthesis constraints in C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2_sdc_constraints_0.v ...Writing to the fileC:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/synth/xst_vlog_bl2cl2.sdc...successful! Generating the fileC:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/synth/xst_vlog_bl2cl2.sdc...successful! Generating the fileC:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/par/xst_vlog_bl2cl2.ucf...successful! Reading the file c:/CAE/Xilinx81i/coregen/ip/xilinx/other/com/xilinx/ip/mig_v1_5/bin/nt/../../data/dlib/spartan3/DDR SDRAM/verilog/rtl/mem_interface_top.v...successful! Generating the file C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/xst_vlog_bl2cl2.v......successful! Allocating pins for the signals..... Verifying proximity rules for local clock distribution... Rule met... generating pinouts for set 0 to 7 Verifying proximity rules for local clock distribution... Rule met... generating pinouts for set 8 to 15 Successfully generated "DDR SDRAM" interface for controller 0. ******************************************* Successfully generated DDR1 interface. Look at C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/rtl/ C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/synth/ C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/docs and C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/par for output files. Run the C:\Designs\Spartan-3E_Starter_Kit\Test_Designs\DDR_MIG\s3e_starter_mig_ddr\xst_vlog_bl2cl2\/xst_vlog_bl2cl2/par/ise_flow_3.bat file to create the ncd file. Pin allocation ...successful. Result: Successful