The Spartan-3E DDR SDRAM controller design has been hardware verified for the following combination: FPGA PART : xc3s500efg320 Frequency in MHz : 133 Speed grade : -4 HDL : verilog/VHDL Memory type component : DDR SDRAM/Components/MT46V16M16TG-5B Bits per strobe : X8 Banks for Data : 3 Data bits : 16 Banks for addr & cntrl : 3 Row address bits : 13 Column address bits : 10 Bank address bits : 2 Synhtesis tools : XST 8.1i SP3 Simulation tools : Modelsim SE 6.1f NOTES: MIG v1.5 won't allow you to specify to use Bank3 for all Address, Data, and Control IO, and therefore much of the .ucf file had to be carefully hand-modified specifically for this board. There were several hand-modifications to the rtl and simulation files required to do to the core targetted on the Spartan-3E Starter Kit board. To view all of these changes, search all rtl and sim files for comment lines that contain "S3E_STARTER". These changes include: * the differential clock buffer IBUFGDS_LVDS in infrastructure_top module has been replaced a single-ended IBUFG to allow the system clock to come from the board's SMA connector. * the loop-back signal is being done using a single IO pin, rather than an output pin, a loop on the board, back into an input pin. Therefore, the nets cntrl0_rst_dqs_div_in and cntrl0_rst_dqs_div_out have been collapsed to single net known as cntrl0_rst_dqs_div. The signal simply loops out through an output buffer, and then back in through the same pin's input buffer. While the actual board loopback length is normally a critical measurement for proper operation of the controller, the loopback was not designed on this board. To mitigate for the effects of this, the delay time to/from the cntrl0_rst_dqs_div pin had to be taken into account, and the data_read_controller had to be very slightly modified. * the system reset had to be reversed in polarity in order to use the board's active-high momentary pushbuttons. As a result, a new top-level signal was created for reset, called "reset", while "reset_in" became it's inverse. * the test bench signal "data_valid" was brought out to a board LED so as to provide a helpful additional flag to check for data read errors. led_error_output is brought to LD0, and data_valid is brought to LD1 on the board. The data comparison in the testbench is only considered to be error-free if LD1 is lightly illuminated (cyclical pulse signal), while LD0 is not illuminated. * the tap values were modified in the cal_ctrl_0 module - these were optimized to achieve maximum system frequency performance in the hardware. Folder xst_vlog_bl2cl2 has the design files generated for verilog, XST, memory components, BL=2 and CL=2 Folder xst_vhdl_bl4cl3 has the design files generated for vhdl (w/verilog testbench and ddr model), XST, memory components, BL=4 and CL=3 The folders have the rtl, par, synth and sim sub folders. There are bit files provided in the par folders. These bit files can be programmed to the Spartan-3E Starter Kit hardware to see the demo. By double clicking the ise_flow_3.bat, one can re-run the synth and par, that re-generates the bit files. The 'include parameter file in the Verilog rtl files has the absolute path, user should change the paths before running the batch files. *****CHIPSCOPE NOTES***** The following steps explain how to load the bit files using Chipscope and to view the expected data (lfsr) vs. the actual read data from the DDR. ************************* Steps to load xst_vlog_bl2cl2_chipscope.bit: (1) Open the chiscope analyzer. (2) Open the project xst_vlog_bl2cl2.cpj in the par directory by selecting File -> Open Project from the menu and give the path to the project file. (3) Activate the cable port by selecting JTAG Chain -> Xilinx Platform USB Cable. Hit 'OK' for the Cable Select screen. (3) Three devices should be recognized and displayed in the pop-up window. Hit "OK". (4) Right click on DEV:0 in the upper left hand "New Project" window and choose "configure" to chose a bit file to assign to this device. (a) The JTAG configuration window pops up. (b) Hit "Select New File" and navigate to the bit File "..\xst_vlog_bl2cl2\xst_vlog_bl2cl2\par\xst_vlog_bl2cl2_chipscope.bit" and hit "OK" If orange DONE LED glows, then device configuration was successful. Apply the reset,with the help of "Button WEST (D18)" push button switch on the board. (5) A window showing the testbench signals will appear. (6) Attach a clock source to the SMA connector on the board, and set the frequency between 80 and 133 MHz. To see the waveforms in the waveform window press Ctrl+F5 or the T! icon in the analyzer window. The LD1 LED should be dimly illuminated to show that there is a valid "DATA_VALID" signal, and the LD0 LED should not be illuminated for the passing case (no errors detected in testbench). (7) Any time that the system frequency is changed, user should reset the design by pressing the reset on "Button WEST (D18)" (8) Double click the trigger_setup in the MyILA0 to change the trigger. (9) The lfsr_data register contains the "expected data" inside the testbench, but bits 0, 8, 16, and 24 are always optimized out during place-and-route. The read_data_reg1 register contains the full read register, while the read_data_reg register has the same bits removed (0, 8, 16, and 24), so that a fair comparison can be seen when using the Chipscope waveform viewer window. Another way to verify whether the test case passed is by observing the onboard LEDs. If "D10" glows continuously then the components test case passed and if "D4" glows continuously then the DIMM test case passed. ************************* Steps to load xst_vhdl_bl4cl3_chipscope.bit: (1) Open the chiscope analyzer. (2) Open the project xst_vhdl_bl4cl3.cpj in the par directory by selecting File -> Open Project from the menu and give the path to the project file. (3) Activate the cable port by selecting JTAG Chain -> Xilinx Platform USB Cable. Hit 'OK' for the Cable Select screen. (3) Three devices should be recognized and displayed in the pop-up window. Hit "OK". (4) Right click on DEV:0 in the upper left hand "New Project" window and choose "configure" to chose a bit file to assign to this device. (a) The JTAG configuration window pops up. (b) Hit "Select New File" and navigate to the bit File "..\xst_vhdl_bl4cl3\xst_vhdl_bl4cl3\par\xst_vhdl_bl4cl3_chipscope.bit" and hit "OK" If orange DONE LED glows, then device configuration was successful. Apply the reset,with the help of "Button WEST (D18)" push button switch on the board. (5) A window showing the testbench signals will appear. (6) Attach a clock source to the SMA connector on the board, and set the frequency between 80 and 133 MHz. To see the waveforms in the waveform window press Ctrl+F5 or the T! icon in the analyzer window. The LD1 LED should be dimly illuminated to show that there is a valid "DATA_VALID" signal, and the LD0 LED should not be illuminated for the passing case (no errors detected in testbench). (7) Any time that the system frequency is changed, user should reset the design by pressing the reset on "Button WEST (D18)" (8) Double click the trigger_setup in the MyILA0 to change the trigger. (9) The lfsr_data register contains the "expected data" inside the testbench, but bits 0, 8, 16, and 24 are always optimized out during place-and-route. The read_data_reg1 register contains the full read register, while the read_data_reg register has the same bits removed (0, 8, 16, and 24), so that a fair comparison can be seen when using the Chipscope waveform viewer window. Another way to verify whether the test case passed is by observing the onboard LEDs. If "D10" glows continuously then the components test case passed and if "D4" glows continuously then the DIMM test case passed.