8-bit R-2R Ladder Digital To Analog Converter with Equal Currents Design and Layout using AMI C5x Process


The project is an 8-bit digital-to-analog converter that utilizes a resister ladder network to divide current with equal current sources, and an operational amplifier to sum these currents and convert them into an output voltage. The use of an R-2R ladder architecture is very useful for binary-weighted currents. However, the R-2R based converter is easy to implement and the resistance ratio is independent of the number of bits the precision of the resistor is significant. Because the resistance of the R-2R architecture must be so closely matched (as close as 0.01% for the LSB on an 8-bit DAC) and the current ratio through the switches is still large the implementation of current sources is needed. With equal current flow through all the switches the architecture will be slower but more stable.

Figure 1 R-2R ladder DAC with equal currents through switches.


The objective of this project is to design an 8-bit R-2R digital-to-analog converter with current sources and implement the design into a CMOS chip using the AMI c5x process. After simulation, testing, design rules check (DRC), and Layout vs. Schematic (LVS) is completed the project will be submitted to MOSIS for fabrication.


The basic principle of this type of R-2R DAC is to split the reference currents equally through the switches.

The current sources that were used were N-type transistors with a size of W/L = 5/1.5. The current sources used a bias generator that produced 1.68V to allow ~80uA of current. The current sources were necessary for the R-2R DAC to work properly due to the switches and the matching of the resistors. The high poly 2 resistance (R) was equal to 4kW . The switches used a pass transistor configuration and had a resistance value of approximately 500W with the size of W/Ln = 25/0.6 and W/Lp = 50/0.6.



Figure 2 Current Sources - to produce equal current flow through all the switches


Figure 3 Bias Generator for current sources (without a resistor)


Figure 4 Pass Transistor Switches W/Ln = 25/0.6 and W/Lp = 50/0.6

The operational amplifier used in the DAC has 3 stages ( Differential input stage, Common source stage and an Output buffer).


Figure 5 Operational Amplifier 3-Stage

Figure 6 Bias Generator for the operational amplifier


 The gain and phase margin of the operation amplifier was found to be 75.88dB and 111 respectively. The configuration used to find the gain and phase can be seen in Figure 6 and a plot of the gain and phase in Figure 7.

Figure 7 Schematic for bode plot


Figure 8 Bode plots - phase margin 111 degrees and gain 75.88dB

Schematic of the R-2R DAC with current sources and the operational amplifier include bias generators.


Figure 9 R-2R DAC with current sources


As mentioned above the operational amplifier simulated to have a gain of 75.88 dB with a phase of 111 . Extensive simulation was done on the 8-bit R-2R DAC. The simulation done was various corner testing. The corners that were tested were the typical (typ), wc1, wc0, Worst Case Power (wcp), Worst Case Speed (wcs), and with variations of the capacitors and resistors in the circuit. The results for the typ, wcp and wcs can be found in Table 1. In Appendix A the plots and simulations to the results in Table 1 can be found.

Table 1

Corner Test

Operating Point


Settling Time

Worst Case Power


3.187 2.5 V





3.666 2.5 V





2.883 2.5 V





Layout and Packaging

The chip will contain two 8 bit DAC and will be packaged in a 40 pin DIP. The pin out can be seen in Figure 10.

Figure 10 Pin out of Two by 8 Bit DAC Layout



Figure 11 Layout of Two by 8 bit DAC with the PADS


Figure 12 Layout of an 8 Bit R2R DAC

Figure 13 Layout of OPAMP

Figure 14 Layout of the OPAMP bias generator

Figure 15 Layout of pass-transistor switches

Figure 16 Layout of the Current Sources


Figure 17 Layout for the Current Source Bias Generator


Figure 18 Layout of Inverter



A counter and an oscilloscope will be used to measure and increment through each of the 256 data points. The data points will be analyzed using Matlab to see the variance of the realistic versus the ideal. Testing the chip will take place eight weeks after it has been submitted to MOSIS.







Appendix A



DAC with Pads

Pass Transistor Switch

Current Sources

Current Source Bias Generator

Opamp w/out Bias Generator

Bias Generator

R-2R D/A Convert


Bode plot schematic


Ramp Down of the R-2R DAC with 8 Bits

Ramp Down

Zoomed in Ramp Down

WCS Ramped Down

WCP Ramped Down

Zoomed in when bits transition from 10000000 01111111

Zoomed in when bits transition from 10000000 01111111

WCS current plot

WCP current plot